1. Field of the Invention
The present invention relates to a high resistivity silicon wafer used as a substrate for a high-frequency integrated circuit device etc., and a method for fabricating the same.
2. Description of the Related Art
With the widespread use or micronization of high-frequency devices and/or the increase in the amount of signal for mobile communication, near-field wireless LAN etc., there has been increasing demand for high-frequency circuits. High resistance is required for high-frequency circuit substrates, for which compound semiconductors such as GaAs have conventionally been adopted frequently. However, compound semiconductor substrates are very expensive.
For such application, CMOS (Complementary Metal Oxide Semiconductor) devices using substrates made of single crystals of silicon obtained by the normal Czochralski method (CZ method) have been considered inappropriate due to large power consumption and high possibility of substrate noise generation. However, as the improvement of micronization technique, designing etc. has been promoted, the use of silicon wafers with high resistivity has been allowing the problems above to be overcome.
The resistivity of high-purity silicon is found to be 2.3×105 Ωcm, which results in too high electrical resistance to be used as a substrate material. Hence, a slight amount of dopant such as boron (B: p type) or phosphorus (P: n type) is added to adjust the resistivity as desired.
Meanwhile, since the increase in the amount of impurities in a semiconductor is likely to reduce the electrical resistance thereof, high resistivity silicon wafers, if necessary, have conventionally been made of single crystals obtained by the Floating Zone method (FZ method) that makes it easy to achieve higher purity. However, the FZ method has difficulties in fabricating large-diameter single crystals and has problems relating to stability of quality and cost, resulting in drawbacks of not allowing an enough response to demand.
In accordance with the CZ method, a single crystal of silicon is fabricated by melting raw material using a quartz crucible and pulling directly from the melt, and thereby contains usually about 20 ppma (16×1018 atoms/cm3 [ASTM F121-1979]) of oxygen eluted from the quartz crucible.
Oxygen contained in such a relatively high concentration as above causes defects in wafer resulting in a faulty characteristic of devices, while in the device fabrication process performs complex functions such as increasing wafer strength to prevent deformation and forming minute defects, in wafer, having gettering effect for trapping mixed heavy metal ions that cause a faulty operation of devices.
As is well known, the resistivity of silicon wafers can be increased by reducing the amount of dopant. However, in the use of single crystals of silicon obtained by the CZ method, inevitably mixed oxygen can change the resistivity significantly. Oxygen atoms are usually electrically neutral in silicon and thereby have no impact on the electrical resistance thereof directly.
However, a long-time heat treatment at a lower temperature range of 300 to 500 degrees C. forms compounds that have failed to be transformed into stable SiO2 precipitates, which emit electrons to show the behavior of donors' nature, being called oxygen donors or thermal donors.
FIG. 1 is a view typically showing the relationship between the generation number of thermal donors and the resistivity of wafers. In the case of low resistivity wafers with a normal resistivity of about 10 Ωcm, the amount of dopant is large enough in comparison with the generation number of thermal donors, whereby thermal donors, even if generated, have a minor impact on the resistivity. However, in the case of high resistivity wafers, the amount of dopant is small, whereby the resistivity can be affected significantly by thermal donors.
Particularly in the case of p types, the conductivity caused by positive holes as acceptor holes disappears due to electron supply from donors resulting in a significant increase in resistivity, and a further increase in the number of donors causes conversion to n type semiconductors, resulting in a reduction in resistivity. Heating process in the temperature range where thermal donors can easily be generated is to be performed necessarily as a heat treatment in the final stage of the device fabrication process.
The generation amount of thermal donors decreases in silicon wafers with low oxygen concentration. Hence, there are proposed methods for fabricating single crystals with low oxygen concentration to reduce oxygen content, such as applying the Magnetic field applied Czochralski method (MCZ method) wherein a single crystal is pulled from molten silicon liquid in a quartz crucible while applying a magnetic field thereto to control the flow, and using a quartz crucible on the inner surface of which is coated SiC.
These methods for oxygen reduction, however, have technical limitations in oxygen reduction, causing also an increase in cost, and further suffer from a problem in that the oxygen reduction causes a reduction in wafer strength, whereby defective products due to deformation can be easily generated in the device fabrication process.
An invention relating to a high resistivity wafer using a single crystal of silicon obtained by the CZ method and eliminating the influence of thermal donors and a method for fabricating the same is disclosed in the brochure of International Patent Publication No. WO 00/55397 (hereinafter referred to as “document 1”). This invention is characterized in that a single crystal with a resistivity of 100 Ωcm or more and an initial interstitial oxygen (soluble oxygen) concentration of 10 to 25 ppma (7.9×1017 to 19.8×1017 atoms/cm3 [ASTM F121-1979]) and with normal oxygen content obtained by the CZ method is processed into a wafer, and then an oxygen precipitate treatment is applied to the wafer to reduce the residual interstitial oxygen concentration to 8 ppma or less (6.4×1017 atoms/cm3 [ASTM F121-1979]). The wafer thus obtained is regarded as to have no reduction in resistivity, due to the prevention of oxygen donor generation by a heat treatment subjected in the device fabrication process.
In the invention above, the heat treatment method for reducing the residual interstitial oxygen concentration down to 8 ppma is considered a fundamental basis of the technology. However, in the document 1 above is described that since oxygen precipitates have only to be formed as a result to reduce the residual interstitial oxygen concentration 8 ppma or less, the heat treatment condition range etc. should not be restricted particularly, having no clear definition.
In an embodiment of the invention are barely shown a two-step heat treatment including a 4-hour heating at 800 degrees C. in oxygen or nitrogen atmosphere and a 16-hour heating at 1000 degrees C. in oxygen atmosphere, and a three-step heat treatment including a 2-hour heating at 650 degrees C. in oxygen atmosphere, a 4-hour heating at 800 degrees C. in the same atmosphere and a 16-hour heating at 1000 degrees C. in oxygen atmosphere.
The DZ-IG (Denuded Zone—Intrinsic Gettering) treatment is generally employed as a method for controlling the presence of oxygen in the wafer thickness direction on which devices are to be formed. This is a heat treatment adapted to prepare the region in the vicinity of the wafer surface in which devices are to be formed, that is, active region as denuded zone (DZ), and to form defects due to oxygen precipitates having a function of trapping heavy metal ions etc. being mixed in the wafer.
Generally, a three-step heat treatment is to be performed, including (1) an oxygen outward diffusion heat treatment at high temperature for forming DZ in the surface region, (2) a low-temperature heat treatment for forming precipitate nuclei (heat treatment for forming oxygen precipitate nuclei) and (3) a middle or high-temperature heat treatment for forming defects due to oxygen precipitates to be operated internally as gettering sites (heat treatment for growing oxygen precipitates).
In Japanese Patent Laid-Open Publication No. 2000-100631 (hereinafter referred to as “document 2”) is disclosed an invention relating to a high resistivity wafer with a resistivity of 100 Ωcm or more to which the DZ-IG treatment is applied, and relating to a condition thereof. This invention is characterized, as is the case with the invention described in the document 1, in that the interstitial oxygen concentration at any portion of the wafer is 8 ppma or less, having DZ in the vicinity of the surface and an oxygen precipitate layer in the bulk portion, and on that basis the width of the transition region between the DZ and the oxygen precipitate layer is 5 μm or less.
In a method for fabricating a wafer according to the invention described in the document 2 above is used a wafer processed from a single crystal with an initial interstitial oxygen concentration of 10 to 25 ppma obtained by the CZ method, and is performed a four-step heat treatment comprising (a) first heat treatment at 950 to 1050 degrees C. for 2 to 5 hours, (b) second heat treatment at 450 to 550 degrees C. for 4 to 5 hours, (c) third heat treatment at 750 to 850 degrees C. for 2 to 8 hours and (d) fourth heat treatment at 950 to 1100 degrees C., to reduce the interstitial oxygen concentration to 8 ppma or less as described above.
In the case above, it would appear that the first heat treatment indicated by (a) is an oxygen outward diffusion heat treatment for forming DZ in the surface region and that the fourth heat treatment indicated by (d) is an oxygen precipitate treatment for forming gettering sites, while (b) and (c) are for performing treatments for forming precipitate nuclei sufficiently to reduce the interstitial oxygen concentration 8 ppma or less assuredly.
However, it is not necessarily easy to reduce the soluble oxygen concentration to 8 ppma or less across the wafer thickness direction by the heat treatments, requiring a lot of man-hours for the heat treatments and resulting in an increase in fabrication cost. In addition, reducing the soluble oxygen concentration results in a great reduction in wafer strength, whereby wafer deformation and/or slip dislocation can easily be generated in a high-temperature heat treatment performed in the device fabrication process even if the number of oxygen donors may be reduced.